Xilinx HDMI RX Subsystem

The Xilinx HDMI RX Subsystem contains several subcores to implement
a HDMI receiver. /hdmi/xilinx-hdmi-rx.c implements a
V4L2 video-capture sub-device for the Xilinx Video IP Pipeline device
(xilinx-vipp).

There are 2 optional HDCP cores that can be included in the IP configuration.
Below provided sample device tree depicts the configuration when both cores are
included. If an optional core is included then corresponding entries for the
core parameters (interrupts, key-management block address) must be included in
the device tree

Note: If HDCP cores are included in the design, the user must provide valid
	  HDCP keys for the encryption to work.

Refer to xlnx,vphy.txt for the phy specifics.

Required Properties:
 - compatible: Should be "xlnx,v-hdmi-rx-ss-3.1".
 - reg: Base address and size of the IP core and hdcp1x key management block
 - reg-names: Identification string for included register blocks
		"hdmi-rxss": Identification string for hdmirx subsystem. Always present
		"hdcp1x-keymngmt": Identification string for Key management block for
			hdcp1x. [Optional]
 - interrupts-parent: phandle for interrupt controller.
 - interrupts: Interrupt numbers for mandatory and optional blocks
 - interrupt-names: Identification string that binds irq number to block
		generating the interrupt
		"irq": interrupt for tx subcore [always present]
		"hdcp14_irq": interrupt for hdcp1.4 core [optional - present if hdcp1x
		is included]
		"hdcp14_timer_irq": interrupt for hdcp1.4 timer [optional - present if
		hdcp1x is included]
		"hdcp22_irq": interrupt for hdcp22 core [optional - present if hdcp22
		is included]
		"hdcp22_timer_irq": interrupt for hdcp2.2 timer [optional - present if
		hdcp22 is included]

 - clocks: phandle of all the clocks required by IP are listed here.
 - clock-names: names of all the clocks required by IP are listed here.
          NOTE: Auto generated DT is providing all the clock names and handles
          reuired by the IP.
          NOTE: Below are the identification string that are always required.
              "s_axi_cpu_aclk", is always required for the axi-lite clock
              "s_axis_video_aclk" is always required for video stream clock

 - phys: phandle for phy lanes registered for hdmi protocol. HDMI always
         require 3 lanes
 - phy-names: The identification string, "hdmi-phy0" and so on

 - xlnx,input-pixels-per-clock: IP configuration for samples/clk (2, 4)
         Note: Only 2 is supported at this time
 - xlnx,max-bits-per-component: The data width per video component (8,10,12,16)
         Note: Only 8 & 10 is supported at this time
 - xlnx,edid-ram-size: Denotes amount of BRAM allocated for EDID in IP
 - xlnx,include-hdcp-1-4: Boolean parameter that denotes if hdcp14 is included.
		If present indicates inclusion of the optional core
 - xlnx,include-hdcp-2-2: Boolean parameter that denotes if hdcp22 is included.
		If present indicates inclusion of the optional core
 - xlnx,audio-enabled: Boolean parameter to convey that design has audio
		functionality.
		If present, indicates optional audio core needed for audio
		usecase is included.
 - xlnx,snd-pcm: Reference to audio formatter block. Add this if, audio formatter
		is going to be used for HDMI audio.
		Needed only if "xlnx,audio-enabled" is included.
 - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt.
          The Rx only has an output port (0).

==Example==
If hdcp1.4 is included in the design then key management block node should be
added to the device tree

	hdcp_keymngmt_blk_1: hdcp_keymngmt_blk_top@88000000 {
		clock-names = "s_axi_aclk", "m_axis_aclk";
		clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
		compatible = "xlnx,hdcp-keymngmt-blk-top-1.0";
		reg = <0x0 0x88000000 0x0 0x10000>;
	};

	v_hdmi_rx_ss: v_hdmi_rx_ss@80000000 {
		compatible = "xlnx,v-hdmi-rx-ss-3.1";
		reg = <0x0 0xa0000000 0x0 0x100000>, <0x0 0xa0270000 0x0 0x10000>;
		reg-names = "hdmi-rxss", "hdcp1x-keymngmt";
		interrupt-parent = <&gic>;
		interrupts = <0 90 4 0 104 4 0 105 4 0 108 4 0 109 4>;
		interrupt-names = "irq", "hdcp14_irq", "hdcp14_timer_irq", "hdcp22_irq", "hdcp22_timer_irq";
		clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk";
		clocks = <&zynqmp_clk 71>, <&misc_clk_1>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 72>;
		phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
		phys = <&vphy_lane0 0 1 1 0>, <&vphy_lane1 0 1 1 0>, <&vphy_lane2 0 1 1 0>;

		xlnx,input-pixels-per-clock = <0x2>;
		xlnx,max-bits-per-component = <0xa>;
		xlnx,edid-ram-size = <0x100>;
		xlnx,include-hdcp-1-4;
		xlnx,include-hdcp-2-2;
		xlnx,audio-enabled;
		xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;

				/* HDMI RX SS -> FB-WR */
				hdmi_rxss_out: endpoint {
					remote-endpoint = <&vcap_hdmi_in>;
				};
			};
		};
	};

	Documentation of "audio_ss_0_audio_formatter_0" node is located
	at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt
